Conventional CMOS SRAM cells typically consist of six transistors: two P channel field effect transistors (PFETs) for a pull-up operation, two N channel field effect transistors (NFETs) for pull down, and two NFETs for input/output (i.e., pass gate) access. The two pass gates are symmetric pass gates, having moderate leakage junctions.
As shown in FIG. 1A, P1 and N1 form an inverter which is cross-coupled with another inverter consisting of P2 and N2. NL and NR are the pass gate access devices which control reading from and writing into the cell. The pass gates NL and NR consist of moderate leakage junctions which contribute to the instability of the device, e.g., shorting, etc.
The corresponding layout for the above circuit is shown in FIG. 1B. The two pull-up PFETs P1 and P2 are referenced by numeral 102, the two pull down NFETs N1 and N2 by 111, and the pass gate NFETs NL and NR by 101. For simplicity sake, metal shapes are not shown. In the particular layout, the word line (WL) is shown at first level metal M1 along the X-direction. The bit lines and the GND line are represented at the second level metal M2 along the Y-direction. Line 121 is the left bit line BL; line 122, the right bit line BR; and line 120, the vertical GND bus. The shape referenced by RX represents the active silicon area; PC, the polysilicon; CA, the contact from the first level metal M1 to PC or RX; and NW, the region for the N-well of the P-channel devices.
A conventional SRAM array consists of m rows and n columns of the aforementioned SRAM cells. Cells of the same row share one WL, while cells of the same column share the same bit line pair, consisting of BL and BR. The aforementioned design is used in many SRAMs, including, e.g., 1 Mega-bit memory having, typically, 1024 by 1024 cells.
During standby, all the WLs are at low (i.e., at GND level) and all bit lines are biased to the standby voltage level (of the power supply) Vdd. Thus, the NFET pass gate devices NL and NR of all the cells are shut off. A data bit 1 is maintained with P1 and N2 on, and P2 and N1 off, such that the left cell node CL is at high (i.e., Vdd) while CR is at low (GND). Correspondingly, a data bit 0 is maintained when P2 and N1 are on, and P1 and N2 off, which forces the right cell node CR to high (i.e., Vdd) and the left node CL to GND. During access time, one WL is selected by being switched on (to Vdd) such that half of the PFET pass gate devices along the selected WL are turned on simultaneously. For each cell along the selected WL, one pass gate device is turned on.
During a read access operation, either BL or BR are pulled down from their high (at Vdd) by the cell. BL is pulled down if the cell is at 0, whereas BR is pulled down if the cell is at 1. A bit select multiplexor then steers the selected bit pair(s) to appropriate sense amplifiers to generate the digital signals for the external circuitry requesting the read memory operation. The sense signals developed along the unselected bit columns are ignored. The cells along the selected WL that were not selected are referred to as the half-selected cells.
During a write access operation, the bit select circuitry steers the input data into the selected bit pairs. To write a 1, BL is driven to high (i.e., to Vdd) and BR to low (i.e., to GND), shutting off N1 and P2, while turning on N2 and P1. To write a 0, BL is forced to low and BR to high. Along the unselected bit columns, BL and BR are coupled to Vdd and are gradually pulled down by the half-selected cells, as described in the read operation. Thus, during a read access operation, all the cells along the selected WL are disturbed since one NFET pass gate device of each SRAM cell remains on.
During a write access, all the half-selected cells are similarly disturbed as during the read operation. When a cell is at 0, the left cell node CL is at GND. When WL is raised to high (i.e., Vdd), the pass gate device NL switches on, raising BL to Vdd and pulling the left cell node up. Thus, NL and N1 act as a potential divider at CL between Vdd and GND. To prevent the node CL from rising beyond the threshold voltage of N2, the conductance of N1 must be larger than the conductance of NL. Otherwise, N2 turns on, pulling down the node CR, switching P1 on, and raising the node CL from GND to Vdd. In such an instance, the cell is disturbed from its 0 state to a 1 state.
Thus, the ratio of the conductance of N1 over the conductance of NL is a basic metric to measure the stability of the SRAM. This ratio is referred to by CMOS SRAM designers as beta or beta ratio. It is defined as the ratio of the conductance of the pull down device 111 over the conductance of pass gate device 101.
There is no precise analytical expression for the conductance of the transistors. It is approximately proportional to m (pw/pl), wherein pl is the device channel length; pw, the device channel width and m, the effective carrier mobility. Accordingly, the beta of the cell can be approximated by the ratio of (m*pw/pl) of transistor N1 and (m*pw/pl) of NL. If N1 and NL have the same channel length, then the beta ratio becomes the ratio of the channel width of N1 over the channel width of NL. Depending on the SRAM application, beta ranges from 1.8 to 3. In general, beta needs to be bigger for faster operations.
Referring back to FIG. 1A, the six-transistor (6-T) cell shown has been the basic structure used in SRAM circuit designs, even though it is much larger than, e.g., a 1-T DRAM. Indeed, the cell size ratio between SRAM and DRAM generally exceeds 8. Many attempts have been made in the past to reduce the size of the SRAM cell. However, these attempts are routinely achieved by trade-offs between certain desirable feature characteristics of the 6-T SRAM cell. By way of example, the cell size can be reduced by removing the pull-up P channel FETs. This replacement introduces significant problems when the cell stability degrades and standby power dissipation increases. A cell read operation becomes destructive, and write back provisions must be introduced. As a result, the cycle time increases significantly and the access power becomes unacceptably large. Further, a standby pull-up current must also be provided to retain the cell data. Thus, the standby power becomes very significant.
Besides the SRAM cell size, other considerations such as stability and power dissipation problems are emerging, as a result of technology down scaling. As the cells shrink in size, the cells are more prone to flipping because of cosmic rays and alpha particles. Accordingly, soft errors have dramatically increased with every new generation. Further, the off currents of the FET devices also increase exponentially because of the shortened channels. Thus, the SRAM cells become too hot and too unstable as the technology continues its scaling down progression by reducing the size of the cell with more advanced lithography and fabrication processes.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.